In various circuit contexts, a load (e.g., an inductor, LC tank, capacitor, speaker, or any other type of load) is driven by a voltage signal that is controlled to have either a logical HIGH (e.g., ‘1’) or LOW (e.g., ‘0’) voltage value. For example, a PMOS transistor and an NMOS transistor may be arranged to provide either the HIGH or LOW signal at a node coupled to the load. Such a PMOS transistor and NMOS transistor are controlled by PMOS and NMOS gate signals, respectively, to conditionally conduct current between source and drain terminals. PMOS and NMOS gate driver circuits are traditionally used to provide such gate signals, so that either the PMOS transistor is an “ON” (conducting) state and the NMOS transistor is in an “OFF” (non-conducting) state, or vice versa.
In order to prevent the PMOS and NMOS transistors from simultaneously being in the conducting state (i.e., both transistors turned on), gate drivers are traditionally designed to meet precise timing requirements. For example, a rise in a PMOS gate signal from LOW to HIGH may be designed to occur a predetermined time before a rise in an NMOS gate signal from LOW to HIGH, so that the time intervals during which the PMOS and NMOS transistors are in the conducting state do not overlap. In order to provide such a non-overlap time between one transistor being turned off and the other being turned on, separate PMOS and NMOS gate drivers have traditionally been required, which has negatively impacted cost, silicon area, power density, and power efficiency.